1. Field of the Invention
This invention relates to microcomputers and, more particularly, to a single-chip microcomputer, in which a CPU, a CPU power source, a RAM, a ROM, a main clock oscillator circuit, a low clock frequency oscillator circuit, etc., are formed on a single chip. More specifically, the invention concerns reduction of power consumption for oscillation.
2. Description of the Prior Art
FIG. 4 shows the construction of an oscillator circuit 1 in a prior art single-chip microcomputer, in which a low clock frequency oscillator circuit at 32.768 Hz, for instance, is provided separately from a main clock oscillator circuit. Reference numerals 2 and 3 designate input and output side pads, respectively, to which an oscillating element such as a crystal oscillator is connected. Numeral 4 designates a MOS inverter, which is constituted by a enhancement N-channel MOS transistor 5 and enhancement P-channel MOS transistor 6. Its gate is connected to the pad 2, and its output terminal is connected to the pad 2, and its output terminal is connected to the pad 3. Numeral 7 designates a CMOS clocked inverter including enhancement N-channel MOS transistors 8 and 9 and enhancement P-channel MOS transistors 10 and 11. The transistors 9 and 10 have their gates connected to the pad 2 and their output terminals connected to the pad 3. A H/L signal 13 is supplied as control signal from a CPU 12 to the clocked inverter 7. The CMOS inverter 14 serves to invert the polarity of the H/L signal 11. The output side pad 3 is connected to the input terminal of a CMOS inverter, the output terminal of which is connected to the input terminal of a CMOS inverter 16.
The operation will now be described. The oscillator circuit has the CMOS inverter 4 and CMOS clocked inverter 7 connected in parallel and the input and output terminals connected to the input and output side pads 2 and 3, respectively. Denoting the gains of the inverter 4 and clocked inverter 7 by 1 and 2, respectively, when the H/L signal from the CPU 12 is "H", at which time the clocked inverter 7 is "on", the gain of the oscillating transistor that is constituted by the inverters 4 and 7 is 1+2. When the H/L signal 13 is "L", the clocked inverter is "off", and the gain of the oscillating transistor at this time is 1. Unless the gain of the oscillating transistor is large, the oscillator circuit 1, although it difficulty starts oscillation, maintains oscillator even if the gain is reduced after the oscillation is stabilized. In the oscillating transistor of the oscillator circuit 1, by setting the gain permitting start of oscillation to be .beta..sub.1 +.beta..sub.2 and setting the gain permitting maintenance of oscillation to be 1, the oscillator circuit can function such that it can readily start oscillation and hold the oscillation current after the stabilization of oscillation to be comparatively low.
Now, a surge protection circuit of the prior art singlechip microcomputer using the oscillator circuit 1, will now be described together with its pattern layout. FIG. 5(a) is an equivalent circuit diagram of the oscillator circuit including the surge protection circuit, and FIG. 5(b) shows an actual pattern layout example, with parts like those in FIG. 4 designated by like reference numerals. Referring to the Figures, the input side pad 2 consists of aluminum and is connected to a resistor 17 consisting of polysilicone or silicide. The outer terminal the resistor 17 is connected to the drain of an N-channel aluminum-gate filed transistor 18. This drain is also connected to a resistor consisting of polysilicone or silicide. Reference numeral 20 designates a parasitic diode which is formed when the aluminum-gate field transistor 18. The other terminal of the resistor 19 is connected to the drain of an N-channel enhancement MOS transistor 21 of polysilicone or silicide and also to the input terminal of the oscillator circuit 1. The output terminal of the oscillator circuit 1 is connected to the output side pad 3 which consists of aluminum. The transistors 18 and 21 have their sources and gates grounded so that they are "off".
The operation will now be described. In the oscillator circuit 1, the resistor 17, transistor 18, parasitic diode 20, resistor 19 and transistor 21 constitute an input protection circuit. The resistor 17 serves to limit current in the field transistor 18 and also alleviate overcurrent in the inrush section. The field transistor 18 functions as a parasitic lateral transistor to cause current escapement, while the parasitic transistor 20 cause current escapement, with reverse breakdown of its PN junction. The transistor 21 serves to clamp voltage applied to the inner circuit with punch-through of parasitic NPN transistor. On the side of the output side pad 3 of the oscillator circuit 1, no particular protective circuit is provided because of a comparative large pattern area in case when the CMOS inverter 4 and CMOS clocked inverter 7 are connected in parallel. More specifically, reference numeral 22 in FIG. 5(b) is a wiring pattern for ground potential Vss, and 23 a wiring pattern for leading a power source voltage Vcc. Between these wiring patterns are formed the pads 2 and 3, resistor 17, transistor 18 and oscillator circuit 1 which occupies a large area.
The low frequency oscillator circuit in the prior art single-chip microcomputer as noted above is constructed such that the gain of the oscillating transistor can be varied to reduce the current consumption at the time of the stable oscillation. However, since the power source voltage of the oscillator circuit 1 consisting of the inverters 4 and 7 is the same as the CPU operation voltage, which may be 2.4 to 5.5 V, the oscillation current can be reduced only down to about 4.0 .mu.A. Further, the surge voltage on the side 3 of the output side pad 3 that can be withstood, is reduced with reduction of the size and gain of the oscillator circuit 1.